Finite State Machines (FSMs) have long been a cornerstone of digital system design, and continuing advancements in logic synthesis have enabled increasingly optimised implementations. At its core, FSM ...

Well, summer has been and gone; and for most of us it was a time to relax and reflect on our working practices. What can we do to achieve better results? And what can we do to break out of the routine ...

While it is tempting to write RTL and let the synthesis tool take over, this isn’t the best way to get the results we want. In this article, we’ll learn how to create complex combinatorial code in ...

All chip designers know that they must take special care to avoid metastability problems when they have multiple, asynchronous clock domains. In contrast, a design in which all clocks are synchronous ...

This paper presents a digital design flow in order to design high performance differential Emitter Coupled Logic (ECL) circuits efficiently. The proposed flow is similar to the ordinary digital CMOS ...